A Low Cost Semiconductor Metallization/ Planarization Process
نویسندگان
چکیده
This paper presents an electrically-mediated process for copper metallization of semiconductor interconnect features. Compared to traditional metallization processes, the proposed electrochemical deposition process uses a singlecomponent bath that contains no difficult-to-control organic accelerators and levelers. The feasibility of the process is demonstrated by copper deposition onto sectioned VLSI wafers. Focus ion beam scanning electron microscopy (FIB-SEM) pictures of metallized interconnect features are presented for feature sizes in the range of 0.25 to 10 μm (~10 to 400 μ-in.).
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